FEATURES OF THE ELLIOTT 502 COMPUTER

Special Features

There are two special features of the 502 which make it eminently suitable for on-line real-time applications.

  1. The first concerns the transfer of information between the 502 and its associated peripheral equipment. There are three types of transfer:
    (a)The direct transfer.
    (b)The control transfer.
    (c)The autonomous data transfer (A.D.T.).
    (a) Direct Transfer
    This is programmed transfer of data. A special instruction is given, the address part of which is used to select the appropriate peripheral device. The data transfer then takes place between the accumulator and the device selected.
    (b) Control Transfer
    This is another programmed transfer, by which the computer acontrols any peripheral equipment. A special instruction is given, part of the address specifying the particular peripheral device, and the other part of the address specifying the operation.

    For example: 

                     74    176
    refers to the tape handler 2 and instructs the magnetic tape device to rewind the magnetic tape back to the start of the tape.

    A control instruction may also be used to indicate an autonomous transfer.

    (c) The Autonomous Data Transfer
    In both the direct and control transfers above, the data transfer is initiated by the program. In Autonomous Data Transfers, the transfer is initiated by the peripheral device. Data are transferred from or to the main store by the particular peripheral device, the demand for this transfer originating in the peripheral equipment. A maximum of twelve peripheral devices have independent A.D.T. facilities, and each transfer may be arranged to consist of one or two 20-bit words, there being no restriction that a device must always initiate the same kind of A.D.T.

    On receipt of the peripheral equipment demand for a data transfer, the 502 completes the instruction it is currently obeying and then attends to the demand. The maximum delay is 30 microseconds (if the present instruction is a square root extraction), and the minimum A.D.T. delay is of the order of 4-7 microseconds.

    In the event of more than one peripheral device demanding a transfer, a system of priorities is used to enable the computer to deal with the most urgent demand first. Each peripheral is allocated a fixed priority, succesive A.D.T. demands being stored first, irrespective of the time lower priorities have been queuing. A queue of A.D.T.'s is dealt with before the computer obeys another program instruction.

    Each A.D.T. device is associated with a fast store location, which contains the address of the main store location holding the data to be transferred. During the execution of an A.D.T. the fast store address is automatically incremented by one so that succesive A.D.T.'s from a particular device refer to consecutive main store locations.

  2. The second special feature of the 502 is the system of allocating the computer programs. Programs may be allocated to any one of eight different levels of urgency. In general, the least urgent level contains the initial input routine, and the most urgent is an error program level.

    Each one of the levels will be in one of the following states:
     (a)One level will be active. This is the level that is currently being obeyed.
    The remaining levels will be either:
    (b)inactive or
    (c)Quiescent.

    A level may be considered to be originally in the quiescent state, this is the normal state in which there is no requirement for any program on that level. On receipt of a stimulus from an external source indicating that action is required on that level, then that level is considered inactive. The change of state from quiescent to inactive may occur at any time. This stimulus is not associated with the A.D.T. demand. It is an independent signal.

    If, as a result of such a stimulus, there is an inactive level of greater urgency than the current active program, a squence of operations is carried out, called a program break, whereby certain relevant machine registers are stored in the fast store, (in fact S, B, A, R), the new level registers are extracted from the fast store and the program on the greater urgency level is carried out.

    When a program on a level is completed and no further action is required, the current active level is returned to the quiescent state, the appropriate registers are stored and a program break occurs to the next lower incative level.

    Sometimes it is neccesary to suspend action on a given level of urgency without returning the level to quiescent, since this state can only be changed by an external stimulus, Action can be suspended by the use of a suppression facility.

    When a level is suppressed, it is treated as if it were quiescent, but on the removal of the suppression, the level returns to either active or inactive, that is the state before it was before suppression. If, when suppression is removed, that level is now the highest urgency inactive, higher than the current active level, a program break will occur.

    Suppression may originate from:
     (a)Manual controls.
    (b)A program addressable register.
    (c)An external device (this is automatic program suppression, and occurs if a preipheral device is selected by a program for a data transfer and the device is already 'busy'.

    In some applications it is neccesary to inhibit a program break, for example in a subroutine which is being used by more than one level, and this can be done by a programming digit in a written instruction. This digit is commonly called the S digit. Should this digit be present, and a program break demand comes up during the obeying of that instruction, the program break will be delayed until the end of the next instruction without an S digit.

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    Page created by Bill Purvis, last update 22nd November 2003
    Contact me at: mailto:bill 'at' beeb.net