I am currently working on reconstructing the logic for the EDSAC Rebuild Project (a project of the Computer Conservation Society). These pages are my personal record of the current status of the logic. It probably won't make much sense unless you know a lot about the internals of EDSAC.
Note: In my parlance, modules are subdivisions of the logic, roughly based on logical units. In some cases they correspond to individual panels, in others they may consist of several panels.
I have re-typed the original Cambridge Edsac Report and produce an HTML version. I am considering re-writing this in the light of present-day understanding and as documentation for the replica.
I have reconstructed the logic for Edsac, based on existing logic diagrams where they still exist. These are a work in progress and may change as I find and fix problems. They have been tested using a home-grown simulator and need to be thought of as an approximation to the original logic. As my simulator is intolerant of timing errors, the logic contains a fair number of delays which are probably not needed in the real machine, as stray, and deliberately added, capacitance will smooth out many of the glitches that my simulator finds a problem.
The logic modules can be viewed here.
Page created by Bill Purvis, last updated 26th February, 2011