Signal | Modules | |

(0)D0 | Start pulse for TCTSU | |

def: | CCU2/R4P2, | |

refs: | CCU3/R4P3, TCT/R4P6, | |

(70)D35 | Last D35 of multiply sequence | |

def: | TCT/R4P6, | |

refs: | CCU8/R5P11, | |

A1-A | ||

def: | Adder/R3P8, | |

refs: | HalfAdder2/R3P7, | |

A1-B | ||

def: | Adder/R3P8, | |

refs: | !!! no references !!! | |

A1-C | ||

def: | HalfAdder2/R3P7, | |

refs: | Adder/R3P8, | |

A1-Sum | ||

def: | HalfAdder2/R3P7, | |

refs: | Adder/R3P8, | |

A2-A | ||

def: | Adder/R3P8, | |

refs: | HalfAdder1/R3P6, | |

A2-B1 | ||

def: | Adder/R3P8, | |

refs: | HalfAdder1/R3P6, | |

A2-B2 | ||

def: | Adder/R3P8, | |

refs: | HalfAdder1/R3P6, | |

A2-C | ||

def: | HalfAdder1/R3P6, | |

refs: | Adder/R3P8, | |

A2-Sum | ||

def: | HalfAdder1/R3P6, | |

refs: | Adder/R3P8, | |

Acc | ||

def: | Acc/R4P4, | |

refs: | ASU1/R3P3, | |

Acc1 | ||

def: | Panel01/R3P4, | |

refs: | Acc/R4P4, ASU2/R3P2, | |

Acc1-xxx | Least significant half of Accumulator | |

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc1Clk | ||

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc1Clr | ||

def: | Acc/R4P4, | |

refs: | Panel01/R3P4, | |

Acc1IG | ||

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc1In | ||

def: | Acc/R4P4, | |

refs: | Panel01/R3P4, Panel01/R3P4, | |

Acc1OG | ||

def: | Acc/R4P4, | |

refs: | Panel01/R3P4, | |

Acc1Out | Memory tank n output | |

def: | Panel01/R3P4, | |

refs: | Acc/R4P4, | |

Acc2 | Monitor most significant half of Accumulator | |

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc2A1 | ||

def: | Panel01/R3P5, | |

refs: | Acc/R4P4, | |

Acc2Clk | ||

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc2Clr | ||

def: | Acc/R4P4, | |

refs: | Panel01/R3P5, | |

Acc2IG | ||

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc2In | ||

def: | Acc/R4P4, | |

refs: | !!! no references !!! | |

Acc2OG | ||

def: | Acc/R4P4, | |

refs: | Panel01/R3P5, | |

Acc2Out | Memory tank n output | |

def: | Panel01/R3P5, | |

refs: | Acc/R4P4, | |

Adder-A | Shifted output to Adder | |

def: | ASU2/R3P2, | |

refs: | Adder/R3P8, | |

Adder-B | Output to Adder (B) | |

def: | CmpCol/R3P10+11, | |

refs: | Adder/R3P8, HalfAdder2/R3P7, | |

Adder-Sum | Output from the Adder | |

def: | Adder/R3P8, | |

refs: | Acc/R4P4, Panel01/R3P5, Panel01/R3P5, | |

BootValid | Monitoring only | |

def: | Starter/F410-13, | |

refs: | !!! no references !!! | |

C1 | Orders A, S, C, V, N | |

def: | OCod/M2P8+9, | |

refs: | CCU4/R5P7, Mcand/R4P8, | |

C10 | Order G | |

def: | OCod/M2P8+9, | |

refs: | Acc/R4P4, CCU10/R3P13, | |

C11 | Order N | |

def: | OCod/M2P8+9, | |

refs: | CCU8/R5P11, | |

C12 | Order X | |

def: | OCod/M2P8+9, | |

refs: | CCU5/R4P5, | |

C13 | Order Y | |

def: | OCod/M2P8+9, | |

refs: | CCU5/R4P5, | |

C14 | Order V | |

def: | OCod/M2P8+9, | |

refs: | CCU8/R5P11, | |

C16 | Order I | |

def: | OCod/M2P8+9, | |

refs: | Tape/F4P7+8, | |

C17 | Orders T, U, I, F, (Starter) | |

def: | OCod/M2P8+9, | |

refs: | MCU/M1P2-4, | |

C17A | ||

def: | OCod/M2P8+9, | |

refs: | TDec0/M3P13, | |

C18 | Order H | |

def: | OCod/M2P8+9, | |

refs: | CCU9/R5P8, Mpier/R4P13, | |

C19 | Orders T, U | |

def: | OCod/M2P8+9, | |

refs: | ASU1/R3P3, CCU9/R5P8, | |

C2 | Order A | |

def: | OCod/M2P8+9, | |

refs: | CmpCol/R3P10+11, | |

C20 | Order T | |

def: | OCod/M2P8+9, | |

refs: | CCU9/R5P8, | |

C21 | Order O | |

def: | OCod/M2P8+9, | |

refs: | Mcand/R4P8, MCU/M1P2-4, Printer/F4P4-6, | |

C22 | Order Z, and illegal orders | |

def: | OCod/M2P8+9, | |

refs: | Controls/M2P10, | |

C24 | Orders C, H | |

def: | OCod/M2P8+9, | |

refs: | !!! no references !!! | |

C25 | Order E | |

def: | OCod/M2P8+9, | |

refs: | Acc/R4P4, CCU10/R3P13, | |

C26 | Orders A, S, C, V, N, H, (Starter) | |

def: | OCod/M2P8+9, | |

refs: | MCU/M1P2-4, | |

C27 | Orders I, O | |

def: | OCod/M2P8+9, | |

refs: | !!! no references !!! | |

C3 | Order S | |

def: | OCod/M2P8+9, | |

refs: | CmpCol/R3P10+11, | |

C4 | Order C | |

def: | OCod/M2P8+9, | |

refs: | CmpCol/R3P10+11, | |

C5 | Order V, N | |

def: | OCod/M2P8+9, | |

refs: | CCU2/R4P2, TCT/R4P6, | |

C6 | Order R, L | |

def: | OCod/M2P8+9, | |

refs: | CCU2/R4P2, CCU3/R4P3, TCT/R4P6, | |

C7 | Order R | |

def: | OCod/M2P8+9, | |

refs: | ASU1/R3P3, CCU2/R4P2, CmpCol/R3P10+11, | |

C8 | Order L | |

def: | OCod/M2P8+9, | |

refs: | ASU1/R3P3, | |

C9 | Orders Y, X | |

def: | OCod/M2P8+9, | |

refs: | CCU5/R4P5, CmpCol/R3P10+11, | |

CCUones | Sign insertion/propagation pulses | |

def: | CCU6/R3P12, | |

refs: | CmpCol/R3P10+11, | |

CG+ | Coincidence Gate (positive) | |

def: | CU/M1P5-6, | |

refs: | Order/M1P8, TDec0/M3P13, | |

CG- | Coincidence Gate (inverse) | |

def: | CU/M1P5-6, | |

refs: | !!! no references !!! | |

ClearFlash | ||

def: | TFL/M3P8-10, | |

refs: | !!! no references !!! | |

Clock | Clock Pulses every 2 usec | |

def: | Clock/F3P11, | |

refs: | Acc/R4P4, ASU1/R3P3, ASU2/R3P2, CCU7/R5P6, CmpCol/R3P10+11, Ctr/M1P7, HalfAdder1/M1P10, HalfAdder1/M1P9, HalfAdder1/R3P6, HalfAdder2/R3P7, Mcand/R4P8, Mpier/R4P13, | |

Order/M1P8, Panel01/R3P4, Panel01/R3P5, SCT/M1P7, TCT/R4P6, TDec1/F1P7, TDec1/F2P7, TDec1/R1P7, TDec1/R2P7, XFR/M2P11-P12, | ||

CLS- | ||

def: | Controls/M2P10, | |

refs: | TDec1/F1P7, TDec1/F2P7, TDec1/R1P7, TDec1/R2P7, | |

Counter | Defines position of words in long tanks | |

def: | Ctr/M1P7, | |

refs: | CU/M1P5-6, | |

CtrClk | ||

def: | Ctr/M1P7, | |

refs: | Panel01/M1P14, | |

CtrClr | ||

def: | Ctr/M1P7, | |

refs: | Panel01/M1P14, | |

CtrHA-A | ||

def: | Ctr/M1P7, | |

refs: | HalfAdder1/M1P10, | |

CtrHA-B1 | ||

def: | Ctr/M1P7, | |

refs: | HalfAdder1/M1P10, | |

CtrHA-B2 | ||

def: | Ctr/M1P7, | |

refs: | HalfAdder1/M1P10, | |

CtrHA-C | ||

def: | HalfAdder1/M1P10, | |

refs: | Ctr/M1P7, | |

CtrHA-Sum | ||

def: | HalfAdder1/M1P10, | |

refs: | Ctr/M1P7, | |

CtrIG | ||

def: | Ctr/M1P7, | |

refs: | Panel01/M1P14, | |

CtrIn | ||

def: | Ctr/M1P7, | |

refs: | Panel01/M1P14, | |

CtrMon | ||

def: | Panel01/M1P14, | |

refs: | !!! no references !!! | |

CtrOG | ||

def: | Ctr/M1P7, | |

refs: | Panel01/M1P14, | |

CtrOut | Memory tank n output | |

def: | Panel01/M1P14, | |

refs: | Ctr/M1P7, | |

D0 | Digit Pulse 0 | |

def: | DPG/F3P7, | |

refs: | CCU10/R3P13, CU/M1P5-6, ECP/F4P9, MCU/M1P2-4, Mpier/R4P13, Order/M1P8, | |

D1 | Digit Pulse 1 | |

def: | DPG/F3P7, | |

refs: | CCU1/R5P9, Ctr/M1P7, CU/M1P5-6, DPG/F3P8, | |

D13 | Clock Pulse at start of each cycle | |

def: | Clock/F3P11, | |

refs: | DPG/F3P2, | |

D14 | Digit Pulse 14 | |

def: | DPG/F3P2, | |

refs: | !!! no references !!! | |

D15 | Digit Pulse 15 | |

def: | DPG/F3P2, | |

refs: | !!! no references !!! | |

D16 | Digit Pulse 16 | |

def: | DPG/F3P2, | |

refs: | !!! no references !!! | |

D17 | Digit Pulse 17 | |

def: | DPG/F3P2, | |

refs: | ASU1/R3P3, DPG/F3P3, | |

D18 | Digit Pulse 18 | |

def: | DPG/F3P3, | |

refs: | CCU1/R5P9, CCU5/R4P5, Controls/M2P10, CU/M1P5-6, ECP/F4P9, MCU/M1P2-4, Order/M1P8, Starter/F410-13, Tape/F4P7+8, | |

D19 | Digit Pulse 19 | |

def: | DPG/F3P3, | |

refs: | Ctr/M1P7, CU/M1P5-6, Starter/F410-13, Tape/F4P7+8, TFL/M3P8-10, | |

D2 | Digit Pulse 2 | |

def: | DPG/F3P8, | |

refs: | CCU10/R3P13, Ctr/M1P7, | |

D20 | Digit Pulse 20 | |

def: | DPG/F3P3, | |

refs: | Starter/F410-13, Tape/F4P7+8, TFL/M3P8-10, | |

D21 | Digit Pulse 21 | |

def: | DPG/F3P3, | |

refs: | DPG/F3P4, Starter/F410-13, Tape/F4P7+8, | |

D22 | Digit Pulse 22 | |

def: | DPG/F3P4, | |

refs: | Starter/F410-13, Tape/F4P7+8, | |

D23 | Digit Pulse 23 | |

def: | DPG/F3P4, | |

refs: | Starter/F410-13, | |

D24 | Digit Pulse 24 | |

def: | DPG/F3P4, | |

refs: | Ctr/M1P7, CU/M1P5-6, Starter/F410-13, | |

D25 | Digit Pulse 25 | |

def: | DPG/F3P4, | |

refs: | DPG/F3P5, Starter/F410-13, TFL/M3P8-10, | |

D26 | Digit Pulse 26 | |

def: | DPG/F3P5, | |

refs: | Starter/F410-13, TFL/M3P8-10, | |

D27 | Digit Pulse 27 | |

def: | DPG/F3P5, | |

refs: | Starter/F410-13, TFL/M3P8-10, | |

D28 | Digit Pulse 28 | |

def: | DPG/F3P5, | |

refs: | Starter/F410-13, TFL/M3P8-10, | |

D29 | Digit Pulse 29 | |

def: | DPG/F3P5, | |

refs: | DPG/F3P6, Starter/F410-13, TFL/M3P8-10, | |

D3 | Digit Pulse 3 | |

def: | DPG/F3P8, | |

refs: | !!! no references !!! | |

D30 | Digit Pulse 30 | |

def: | DPG/F3P6, | |

refs: | Printer/F4P4-6, Starter/F410-13, | |

D31 | Digit Pulse 31 | |

def: | DPG/F3P6, | |

refs: | OFL/M3P2-4, Printer/F4P4-6, Starter/F410-13, | |

D32 | Digit Pulse 32 | |

def: | DPG/F3P6, | |

refs: | OFL/M3P2-4, Printer/F4P4-6, Starter/F410-13, | |

D33 | Digit Pulse 33 | |

def: | DPG/F3P6, | |

refs: | DPG/F3P7, OFL/M3P2-4, Printer/F4P4-6, Starter/F410-13, | |

D34 | Digit Pulse 34 | |

def: | DPG/F3P7, | |

refs: | OFL/M3P2-4, Printer/F4P4-6, Starter/F410-13, | |

D35 | Digit Pulse 35 | |

def: | DPG/F3P7, | |

refs: | ASU1/R3P3, CCU1/R5P9, CCU10/R3P13, CCU2/R4P2, Controls/M2P10, OFL/M3P2-4, Printer/F4P4-6, TCT/R4P6, | |

D4 | Digit Pulse 4 | |

def: | DPG/F3P8, | |

refs: | !!! no references !!! | |

D5 | Digit Pulse 5 | |

def: | DPG/F3P8, | |

refs: | DPG/F3P9, | |

D6 | Digit Pulse 6 | |

def: | DPG/F3P9, | |

refs: | CU/M1P5-6, | |

D7 | Digit Pulse 7 | |

def: | DPG/F3P9, | |

refs: | !!! no references !!! | |

D8 | Digit Pulse 8 | |

def: | DPG/F3P9, | |

refs: | !!! no references !!! | |

D9 | Digit Pulse 9 | |

def: | DPG/F3P9, | |

refs: | !!! no references !!! | |

Da | Sign test of Multiplicand (via CCU2) | |

def: | TCT/R4P6, | |

refs: | CCU2/R4P2, CCU8/R5P11, | |

Da(M) | Sign test pulse for Multiplicand | |

def: | CCU2/R4P2, | |

refs: | Mcand/R4P8, | |

Da(N) | Result of test Multiplicand sign | |

def: | Mcand/R4P8, | |

refs: | CCU1/R5P9, CCU7/R5P6, | |

Ds | Sign test for right shifts | |

def: | CCU2/R4P2, | |

refs: | Acc/R4P4, | |

Ds(R) | Sign bit propagation for right shifts | |

def: | Acc/R4P4, | |

refs: | CCU8/R5P11, | |

Dv | Sign test pulse for E order | |

def: | CCU10/R3P13, | |

refs: | Acc/R4P4, | |

Dv(D) | Jump condition satisfied | |

def: | Acc/R4P4, | |

refs: | CCU10/R3P13, MCU/M1P2-4, | |

Dx | Digit testing pulse for multiplies | |

def: | TCT/R4P6, | |

refs: | Mpier/R4P13, | |

Dx(M) | response to multiplier digit testing | |

def: | Mpier/R4P13, | |

refs: | CCU7/R5P6, | |

Dy | Resetting pulse after addition of partial product | |

def: | TCT/R4P6, | |

refs: | CCU1/R5P9, CCU3/R4P3, CCU7/R5P6, | |

EngMode | ||

def: | ECP/F4P9, | |

refs: | Order/M1P8, Starter/F410-13, | |

EngMode- | ||

def: | ECP/F4P9, | |

refs: | MCU/M1P2-4, SCT/M1P7, TDec0/M3P13, | |

EngRst | ||

def: | Controls/M2P10, | |

refs: | CU/M1P5-6, MCU/M1P2-4, | |

EP | Combined End Pulse, terminates all orders | |

def: | CCU6/R3P12, | |

refs: | Controls/M2P10, MCU/M1P2-4, Order/M1P8, SCT/M1P7, | |

EP0 | End Pulse terminates Roundoff orders | |

def: | CCU5/R4P5, | |

refs: | CCU6/R3P12, | |

EP1 | End pulse for multiply | |

def: | CCU8/R5P11, | |

refs: | CCU6/R3P12, | |

EP10 | End Pulse from Printer | |

def: | Printer/F4P4-6, | |

refs: | CCU6/R3P12, | |

EP11 | End Pulse to get things started from Frigs | |

def: | Controls/M2P10, | |

refs: | CCU6/R3P12, | |

EP2 | End Pulse 2 terminates shifts | |

def: | CCU3/R4P3, | |

refs: | CCU6/R3P12, | |

EP3 | End Pulse for Addition and Subtraction | |

def: | CCU4/R5P7, | |

refs: | CCU6/R3P12, | |

EP4 | End Pulse for load multiplier order | |

def: | Mpier/R4P13, | |

refs: | CCU6/R3P12, | |

EP5 | End pulse 5 for transfers | |

def: | CCU10/R3P13, | |

refs: | CCU6/R3P12, | |

EP6 | End Pulse for store and clear | |

def: | CCU9/R5P8, | |

refs: | CCU6/R3P12, | |

EP8 | End Pulse from Reader | |

def: | Tape/F4P7+8, | |

refs: | CCU6/R3P12, | |

EP9 | ||

def: | Starter/F410-13, | |

refs: | CCU6/R3P12, | |

EPSEP | ||

def: | Controls/M2P10, | |

refs: | OFL/M3P2-4, TFL/M3P8-10, | |

evD0 | D0 during even cycles | |

def: | CCU1/R5P9, | |

refs: | CCU2/R4P2, CCU3/R4P3, CCU4/R5P7, CCU5/R4P5, CCU8/R5P11, CCU9/R5P8, | |

evD1 | D1 during even cycles | |

def: | CCU1/R5P9, | |

refs: | Adder/R3P8, CCU3/R4P3, CCU9/R5P8, | |

evD1Dz | Early D1 during even cycles to stop inserting ones | |

def: | CCU1/R5P9, | |

refs: | CmpCol/R3P10+11, | |

evD35 | D35 during even cycles | |

def: | CCU1/R5P9, | |

refs: | !!! no references !!! | |

F1+ | Word length control to XFR | |

def: | TFL/M3P8-10, | |

refs: | XFR/M2P11-P12, | |

F1- | Buffered inverse word length control | |

def: | TFL/M3P8-10, | |

refs: | ASU1/R3P3, CU/M1P5-6, | |

F10+ | Tank address bit 10 | |

def: | TFL/M3P8-10, | |

refs: | TDec0/M3P13, | |

F11+ | Tank address bit 11 | |

def: | TFL/M3P8-10, | |

refs: | TDec0/M3P13, | |

F13+ | Order bit 00001 | |

def: | OFL/M3P2-4, | |

refs: | ODec2/M2P2, ODec2/M2P3, ODec2/M2P5, ODec2/M2P6, | |

F13- | Order bits !00001 | |

def: | OFL/M3P2-4, | |

refs: | ODec2/M2P2, ODec2/M2P3, ODec2/M2P5, ODec2/M2P6, | |

F14+ | Order bit 00010 | |

def: | OFL/M3P2-4, | |

refs: | ODec2/M2P2, ODec2/M2P3, ODec2/M2P5, ODec2/M2P6, | |

F14- | Order bits !00010 | |

def: | OFL/M3P2-4, | |

refs: | ODec2/M2P2, ODec2/M2P3, ODec2/M2P5, ODec2/M2P6, | |

F15+ | Order bit 00100 | |

def: | OFL/M3P2-4, | |

refs: | ODec2/M2P2, ODec2/M2P3, ODec2/M2P5, ODec2/M2P6, | |

F15- | Orders bit !00100 | |

def: | OFL/M3P2-4, | |

refs: | ODec2/M2P2, ODec2/M2P3, ODec2/M2P5, ODec2/M2P6, | |

F16+ | Order bit 01000 | |

def: | OFL/M3P2-4, | |

refs: | ODec1/M3P5, | |

F16- | Orders bits !01000 | |

def: | OFL/M3P2-4, | |

refs: | ODec1/M3P5, | |

F17+ | Order bit 10000 | |

def: | OFL/M3P2-4, | |

refs: | ODec1/M3P5, | |

F17- | Orders !10000 | |

def: | OFL/M3P2-4, | |

refs: | ODec1/M3P5, | |

F1Clock | Buffered clock for rack F1 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P10, Panel01/F1P11, Panel01/F1P12, Panel01/F1P13, Panel01/F1P2, Panel01/F1P3, Panel01/F1P4, Panel01/F1P5, | |

F1DnDecIn | Write gate to lower panels | |

def: | TDec1/F1P7, | |

refs: | TDist/F1P8, | |

F1DnDecOut | Read gate to lower panels | |

def: | TDec1/F1P7, | |

refs: | TDist/F1P8, | |

F1DnF7+ | Gate to lower tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P6, | |

F1DnF7- | Inverse gate to lower tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P6, | |

F1DnF8+ | Gate to lower tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P6, | |

F1DnF8- | Inverse gate to lower tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P6, | |

F1DnMOBT0 | Memory tank n output | |

def: | Panel01/F1P2, | |

refs: | TDec1/F1P7, | |

F1DnMOBT1 | Memory tank n output | |

def: | Panel01/F1P3, | |

refs: | TDec1/F1P7, | |

F1DnMOBT2 | Memory tank n output | |

def: | Panel01/F1P4, | |

refs: | TDec1/F1P7, | |

F1DnMOBT3 | Memory tank n output | |

def: | Panel01/F1P5, | |

refs: | TDec1/F1P7, | |

F1DnT0Clr | Clear gate to tank 4 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P2, | |

F1DnT0in | Gate input to tank 0 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P2, TDec1/F1P7, | |

F1DnT0out | Gate output of tank 0 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P2, | |

F1DnT1Clr | Clear gate to tank 5 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P3, | |

F1DnT1in | Gate input to tank 1 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P3, TDec1/F1P7, | |

F1DnT1out | Gate output of tank 1 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P3, | |

F1DnT2Clr | Clear gate to tank 6 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P4, | |

F1DnT2in | Gate input to tank 2 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P4, TDec1/F1P7, | |

F1DnT2out | Gate output of tank 2 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P4, | |

F1DnT3Clr | Clear gate to tank 7 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P5, | |

F1DnT3in | Gate input to tank 3 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P5, TDec1/F1P7, | |

F1DnT3out | Gate output of tank 3 | |

def: | TFinal/F1P6, | |

refs: | Panel01/F1P5, | |

F1DnTIn | Buffered gate to lower TFinal | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P6, | |

F1DnTOut | Buffered gate to lower TFinal | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P6, | |

F1MIBs | Buffered MIB to memory panels in this rack | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P10, Panel01/F1P11, Panel01/F1P12, Panel01/F1P13, Panel01/F1P2, Panel01/F1P3, Panel01/F1P4, Panel01/F1P5, | |

F1MOB | Combined output from tanks in this rack | |

def: | TDec1/F1P7, | |

refs: | XFR/M2P11-P12, | |

F1Read | Read gate to rack F1 | |

def: | TDec0/M3P13, | |

refs: | TDec1/F1P7, | |

F1UpDecIn | Write gate to upper panels | |

def: | TDec1/F1P7, | |

refs: | TDist/F1P8, | |

F1UpDecOut | Read gate to upper panels | |

def: | TDec1/F1P7, | |

refs: | TDist/F1P8, | |

F1UpF7+ | Gate to upper tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P9, | |

F1UpF7- | Inverse gate to upper tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P9, | |

F1UpF8+ | Gate to upper tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P9, | |

F1UpF8- | Inverse gate to upper tank decoder | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P9, | |

F1UpMOBT0 | Memory tank n output | |

def: | Panel01/F1P10, | |

refs: | TDec1/F1P7, | |

F1UpMOBT1 | Memory tank n output | |

def: | Panel01/F1P11, | |

refs: | TDec1/F1P7, | |

F1UpMOBT2 | Memory tank n output | |

def: | Panel01/F1P12, | |

refs: | TDec1/F1P7, | |

F1UpMOBT3 | Memory tank n output | |

def: | Panel01/F1P13, | |

refs: | TDec1/F1P7, | |

F1UpT0Clr | Clear gate to tank 0 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P10, | |

F1UpT0in | Gate input to tank 0 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P10, TDec1/F1P7, | |

F1UpT0out | Gate output of tank 0 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P10, | |

F1UpT1Clr | Clear gate to tank 1 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P11, | |

F1UpT1in | Gate input to tank 1 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P11, TDec1/F1P7, | |

F1UpT1out | Gate output of tank 1 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P11, | |

F1UpT2Clr | Clear gate to tank 2 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P12, | |

F1UpT2in | Gate input to tank 2 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P12, TDec1/F1P7, | |

F1UpT2out | Gate output of tank 2 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P12, | |

F1UpT3Clr | Clear gate to tank 3 | |

def: | TDec1/F1P7, | |

refs: | Panel01/F1P13, | |

F1UpT3in | Gate input to tank 3 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P13, TDec1/F1P7, | |

F1UpT3out | Gate output of tank 3 | |

def: | TFinal/F1P9, | |

refs: | Panel01/F1P13, | |

F1UpTIn | Buffered gate to upper TFinal | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P9, | |

F1UpTOut | Buffered gate to upper TFinal | |

def: | TDist/F1P8, | |

refs: | TFinal/F1P9, | |

F1Write | Write gate to rack F1 | |

def: | TDec0/M3P13, | |

refs: | TDec1/F1P7, | |

F2+ | Odd/Even address bit to XFR | |

def: | TFL/M3P8-10, | |

refs: | XFR/M2P11-P12, | |

F2Clock | Buffered clock for rack F2 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P10, Panel01/F2P11, Panel01/F2P12, Panel01/F2P13, Panel01/F2P2, Panel01/F2P3, Panel01/F2P4, Panel01/F2P5, | |

F2DnDecIn | Write gate to lower panels | |

def: | TDec1/F2P7, | |

refs: | TDist/F2P8, | |

F2DnDecOut | Read gate to lower panels | |

def: | TDec1/F2P7, | |

refs: | TDist/F2P8, | |

F2DnF7+ | Gate to lower tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P6, | |

F2DnF7- | Inverse gate to lower tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P6, | |

F2DnF8+ | Gate to lower tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P6, | |

F2DnF8- | Inverse gate to lower tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P6, | |

F2DnMOBT0 | Memory tank n output | |

def: | Panel01/F2P2, | |

refs: | TDec1/F2P7, | |

F2DnMOBT1 | Memory tank n output | |

def: | Panel01/F2P3, | |

refs: | TDec1/F2P7, | |

F2DnMOBT2 | Memory tank n output | |

def: | Panel01/F2P4, | |

refs: | TDec1/F2P7, | |

F2DnMOBT3 | Memory tank n output | |

def: | Panel01/F2P5, | |

refs: | TDec1/F2P7, | |

F2DnT0Clr | Clear gate to tank 4 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P2, | |

F2DnT0in | Gate input to tank 0 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P2, TDec1/F2P7, | |

F2DnT0out | Gate output of tank 0 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P2, | |

F2DnT1Clr | Clear gate to tank 5 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P3, | |

F2DnT1in | Gate input to tank 1 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P3, TDec1/F2P7, | |

F2DnT1out | Gate output of tank 1 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P3, | |

F2DnT2Clr | Clear gate to tank 6 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P4, | |

F2DnT2in | Gate input to tank 2 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P4, TDec1/F2P7, | |

F2DnT2out | Gate output of tank 2 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P4, | |

F2DnT3Clr | Clear gate to tank 7 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P5, | |

F2DnT3in | Gate input to tank 3 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P5, TDec1/F2P7, | |

F2DnT3out | Gate output of tank 3 | |

def: | TFinal/F2P6, | |

refs: | Panel01/F2P5, | |

F2DnTIn | Buffered gate to lower TFinal | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P6, | |

F2DnTOut | Buffered gate to lower TFinal | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P6, | |

F2MIBs | Buffered MIB to memory panels in this rack | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P10, Panel01/F2P11, Panel01/F2P12, Panel01/F2P13, Panel01/F2P2, Panel01/F2P3, Panel01/F2P4, Panel01/F2P5, | |

F2MOB | Combined output from tanks in this rack | |

def: | TDec1/F2P7, | |

refs: | XFR/M2P11-P12, | |

F2Read | Read gate to rack F2 | |

def: | TDec0/M3P13, | |

refs: | TDec1/F2P7, | |

F2UpDecIn | Write gate to upper panels | |

def: | TDec1/F2P7, | |

refs: | TDist/F2P8, | |

F2UpDecOut | Read gate to upper panels | |

def: | TDec1/F2P7, | |

refs: | TDist/F2P8, | |

F2UpF7+ | Gate to upper tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P9, | |

F2UpF7- | Inverse gate to upper tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P9, | |

F2UpF8+ | Gate to upper tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P9, | |

F2UpF8- | Inverse gate to upper tank decoder | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P9, | |

F2UpMOBT0 | Memory tank n output | |

def: | Panel01/F2P10, | |

refs: | TDec1/F2P7, | |

F2UpMOBT1 | Memory tank n output | |

def: | Panel01/F2P11, | |

refs: | TDec1/F2P7, | |

F2UpMOBT2 | Memory tank n output | |

def: | Panel01/F2P12, | |

refs: | TDec1/F2P7, | |

F2UpMOBT3 | Memory tank n output | |

def: | Panel01/F2P13, | |

refs: | TDec1/F2P7, | |

F2UpT0Clr | Clear gate to tank 0 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P10, | |

F2UpT0in | Gate input to tank 0 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P10, TDec1/F2P7, | |

F2UpT0out | Gate output of tank 0 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P10, | |

F2UpT1Clr | Clear gate to tank 1 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P11, | |

F2UpT1in | Gate input to tank 1 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P11, TDec1/F2P7, | |

F2UpT1out | Gate output of tank 1 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P11, | |

F2UpT2Clr | Clear gate to tank 2 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P12, | |

F2UpT2in | Gate input to tank 2 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P12, TDec1/F2P7, | |

F2UpT2out | Gate output of tank 2 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P12, | |

F2UpT3Clr | Clear gate to tank 3 | |

def: | TDec1/F2P7, | |

refs: | Panel01/F2P13, | |

F2UpT3in | Gate input to tank 3 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P13, TDec1/F2P7, | |

F2UpT3out | Gate output of tank 3 | |

def: | TFinal/F2P9, | |

refs: | Panel01/F2P13, | |

F2UpTIn | Buffered gate to upper TFinal | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P9, | |

F2UpTOut | Buffered gate to upper TFinal | |

def: | TDist/F2P8, | |

refs: | TFinal/F2P9, | |

F2Write | Write gate to rack F2 | |

def: | TDec0/M3P13, | |

refs: | TDec1/F2P7, | |

F7+ | Tank address bit 7 | |

def: | TFL/M3P8-10, | |

refs: | TDist/F1P8, TDist/F2P8, TDist/R1P8, TDist/R2P8, | |

F8+ | Tank address bit 8 | |

def: | TFL/M3P8-10, | |

refs: | TDist/F1P8, TDist/F2P8, TDist/R1P8, TDist/R2P8, | |

F9+ | Tank address bit 9 | |

def: | TFL/M3P8-10, | |

refs: | TDec1/F1P7, TDec1/F2P7, TDec1/R1P7, TDec1/R2P7, | |

fb1 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

fb2 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

fb3 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

fb4 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

fb5 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

G1+ | Odd cycles gate | |

def: | CCU1/R5P9, | |

refs: | Acc/R4P4, | |

G1- | Even cycles gate | |

def: | CCU1/R5P9, | |

refs: | Acc/R4P4, | |

G10- | Multiplier Clear gate | |

def: | CCU9/R5P8, | |

refs: | Mpier/R4P13, | |

G11- | Multiplicand Clear gate | |

def: | CCU9/R5P8, | |

refs: | Mcand/R4P8, | |

G12 | Phase I Gate | |

def: | MCU/M1P2-4, | |

refs: | Mcand/R4P8, Order/M1P8, SCT/M1P7, Starter/F410-13, | |

G13 | Phase II Gate | |

def: | MCU/M1P2-4, | |

refs: | ASU1/R3P3, Mcand/R4P8, ODec1/M3P5, Order/M1P8, TDec0/M3P13, TFL/M3P8-10, | |

G2+ | Multiplicand and shifting gate | |

def: | TCT/R4P6, | |

refs: | Mcand/R4P8, | |

G2- | Inverse Multiplicand and shifting gate | |

def: | TCT/R4P6, | |

refs: | Mcand/R4P8, | |

G3+ | Multiplicand output gate during multiplication | |

def: | CCU7/R5P6, | |

refs: | Mcand/R4P8, | |

G4+ | Complementer gate (+) | |

def: | CCU8/R5P11, | |

refs: | CmpCol/R3P10+11, | |

G4- | Complementer gate (-) | |

def: | CCU8/R5P11, | |

refs: | CmpCol/R3P10+11, | |

G5 | Accumulator shifting gate | |

def: | CCU3/R4P3, | |

refs: | ASU1/R3P3, CCU8/R5P11, | |

G6+ | Multiplicand output gate for A, S and C orders | |

def: | CCU4/R5P7, | |

refs: | Mcand/R4P8, | |

G8 | Inhibit Add/Subtract logic in CCU4 | |

def: | CCU2/R4P2, | |

refs: | CCU4/R5P7, | |

G9- | Accumulator Clear gate | |

def: | CCU9/R5P8, | |

refs: | ASU2/R3P2, | |

GateValid | ||

def: | Starter/F410-13, | |

refs: | !!! no references !!! | |

IIClr- | ||

def: | Starter/F410-13, | |

refs: | SCT/M1P7, | |

IIClrCtr- | ||

def: | Starter/F410-13, | |

refs: | Ctr/M1P7, | |

JPrtBusy | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

JRdrBusy | ||

def: | Tape/F4P7+8, | |

refs: | !!! no references !!! | |

Magnet1 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

Magnet2 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

Magnet3 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

Magnet4 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

Magnet5 | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

MagnetStart | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

MCAA1 | ||

def: | Panel01/R4P10, | |

refs: | Mcand/R4P8, | |

MCAClk | ||

def: | Mcand/R4P8, | |

refs: | Panel01/R4P10, | |

MCAClr | ||

def: | Mcand/R4P8, | |

refs: | Panel01/R4P10, | |

MCAIG | ||

def: | Mcand/R4P8, | |

refs: | Panel01/R4P10, | |

MCAIn | ||

def: | Mcand/R4P8, | |

refs: | Panel01/R4P10, | |

Mcand | Multiplicand output (gated) | |

def: | Mcand/R4P8, | |

refs: | CmpCol/R3P10+11, | |

McandIn | Access to data gpoing into the Multiplicand | |

def: | Mcand/R4P8, | |

refs: | CCU2/R4P2, | |

Mcand~ | Monitoring output from Multiplicand (ungated) | |

def: | Mcand/R4P8, | |

refs: | !!! no references !!! | |

MCAOG | ||

def: | Mcand/R4P8, | |

refs: | Panel01/R4P10, | |

MCAout | Memory tank n output | |

def: | Panel01/R4P10, | |

refs: | Mcand/R4P8, | |

MIB | Main Input Bus to Stores | |

def: | XFR/M2P11-P12, | |

refs: | Mcand/R4P8, Mpier/R4P13, Printer/F4P4-6, TDec1/F1P7, TDec1/F2P7, TDec1/R1P7, TDec1/R2P7, | |

MOB | Monitor Main Output Bus from Units | |

def: | XFR/M2P11-P12, | |

refs: | Order/M1P8, | |

MOB10 | Output from Starter Unit to MOB | |

def: | Starter/F410-13, | |

refs: | XFR/M2P11-P12, | |

MOB11 | Data from printer to MOB (F order) | |

def: | Printer/F4P4-6, | |

refs: | XFR/M2P11-P12, | |

MOB8 | Accumulator output to Store via MOB | |

def: | ASU1/R3P3, | |

refs: | XFR/M2P11-P12, | |

MOB9 | Data output from Reader to MOB | |

def: | Tape/F4P7+8, | |

refs: | XFR/M2P11-P12, | |

mon1 | ||

def: | Panel01/F1P10, | |

refs: | !!! no references !!! | |

mon10 | ||

def: | Panel01/F2P11, | |

refs: | !!! no references !!! | |

mon11 | ||

def: | Panel01/F2P12, | |

refs: | !!! no references !!! | |

mon12 | ||

def: | Panel01/F2P13, | |

refs: | !!! no references !!! | |

mon13 | ||

def: | Panel01/F2P2, | |

refs: | !!! no references !!! | |

mon14 | ||

def: | Panel01/F2P3, | |

refs: | !!! no references !!! | |

mon15 | ||

def: | Panel01/F2P4, | |

refs: | !!! no references !!! | |

mon16 | ||

def: | Panel01/F2P5, | |

refs: | !!! no references !!! | |

mon17 | ||

def: | Panel01/R1P10, | |

refs: | !!! no references !!! | |

mon18 | ||

def: | Panel01/R1P11, | |

refs: | !!! no references !!! | |

mon19 | ||

def: | Panel01/R1P12, | |

refs: | !!! no references !!! | |

mon2 | ||

def: | Panel01/F1P11, | |

refs: | !!! no references !!! | |

mon20 | ||

def: | Panel01/R1P13, | |

refs: | !!! no references !!! | |

mon21 | ||

def: | Panel01/R1P2, | |

refs: | !!! no references !!! | |

mon22 | ||

def: | Panel01/R1P3, | |

refs: | !!! no references !!! | |

mon23 | ||

def: | Panel01/R1P4, | |

refs: | !!! no references !!! | |

mon24 | ||

def: | Panel01/R1P5, | |

refs: | !!! no references !!! | |

mon25 | ||

def: | Panel01/R2P10, | |

refs: | !!! no references !!! | |

mon26 | ||

def: | Panel01/R2P11, | |

refs: | !!! no references !!! | |

mon27 | ||

def: | Panel01/R2P12, | |

refs: | !!! no references !!! | |

mon28 | ||

def: | Panel01/R2P13, | |

refs: | !!! no references !!! | |

mon29 | ||

def: | Panel01/R2P2, | |

refs: | !!! no references !!! | |

mon3 | ||

def: | Panel01/F1P12, | |

refs: | !!! no references !!! | |

mon30 | ||

def: | Panel01/R2P3, | |

refs: | !!! no references !!! | |

mon31 | ||

def: | Panel01/R2P4, | |

refs: | !!! no references !!! | |

mon32 | ||

def: | Panel01/R2P5, | |

refs: | !!! no references !!! | |

mon4 | ||

def: | Panel01/F1P13, | |

refs: | !!! no references !!! | |

mon5 | ||

def: | Panel01/F1P2, | |

refs: | !!! no references !!! | |

mon6 | ||

def: | Panel01/F1P3, | |

refs: | !!! no references !!! | |

mon7 | ||

def: | Panel01/F1P4, | |

refs: | !!! no references !!! | |

mon8 | ||

def: | Panel01/F1P5, | |

refs: | !!! no references !!! | |

mon9 | ||

def: | Panel01/F2P10, | |

refs: | !!! no references !!! | |

Mpier | Multiplier output for monitoring | |

def: | Mpier/R4P13, | |

refs: | CmpCol/R3P10+11, | |

MSUA1 | ||

def: | Panel01/R4P12, | |

refs: | Mpier/R4P13, | |

MSUClk | ||

def: | Mpier/R4P13, | |

refs: | Panel01/R4P12, | |

MSUClr | ||

def: | Mpier/R4P13, | |

refs: | Panel01/R4P12, | |

MSUIG | ||

def: | Mpier/R4P13, | |

refs: | Panel01/R4P12, | |

MSUIn | ||

def: | Mpier/R4P13, | |

refs: | Panel01/R4P12, | |

MSUOG | ||

def: | Mpier/R4P13, | |

refs: | Panel01/R4P12, | |

MSUout | Memory tank n output | |

def: | Panel01/R4P12, | |

refs: | Mpier/R4P13, | |

oddD0 | D0 during odd cycles | |

def: | CCU1/R5P9, | |

refs: | CCU4/R5P7, CCU5/R4P5, CCU9/R5P8, | |

oddD18 | ||

def: | CCU1/R5P9, | |

refs: | !!! no references !!! | |

oddD35 | D35 during odd cycles | |

def: | CCU1/R5P9, | |

refs: | CCU7/R5P6, CCU8/R5P11, | |

ODy0 | Decode for orders 00??? | |

def: | ODec1/M3P5, | |

refs: | ODec2/M2P2, | |

ODy1 | Decode for orders 01??? | |

def: | ODec1/M3P5, | |

refs: | ODec2/M2P3, | |

ODy2 | Decode for orders 10??? | |

def: | ODec1/M3P5, | |

refs: | ODec2/M2P5, | |

ODy3 | Decode for orders 11??? | |

def: | ODec1/M3P5, | |

refs: | ODec2/M2P6, | |

Ones1 | Sign propagation for multiplies | |

def: | CCU7/R5P6, | |

refs: | CCU6/R3P12, | |

Ones2 | Sign propagation | |

def: | CCU8/R5P11, | |

refs: | CCU6/R3P12, | |

Ones4 | Add one for Rounding | |

def: | CCU5/R4P5, | |

refs: | CCU6/R3P12, | |

OP-A | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-B | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-Blank | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-C | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-D | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-Delta | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-E | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-Erase | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-F | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, Printer/F4P4-6, | |

OP-G | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-H | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-I | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-J | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-K | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-L | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-M | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-N | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-O | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-P | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-Phi | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-Pi | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-Q | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-R | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-S | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

OP-T | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-Theta | ||

def: | ODec2/M2P5, | |

refs: | OCod/M2P8+9, | |

OP-U | ||

def: | ODec2/M2P2, | |

refs: | CCU9/R5P8, OCod/M2P8+9, | |

OP-V | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-W | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-X | ||

def: | ODec2/M2P6, | |

refs: | OCod/M2P8+9, | |

OP-Y | ||

def: | ODec2/M2P2, | |

refs: | OCod/M2P8+9, | |

OP-Z | ||

def: | ODec2/M2P3, | |

refs: | OCod/M2P8+9, | |

ORDA1 | ||

def: | Panel01/M1P11, | |

refs: | Order/M1P8, | |

ORDClk | ||

def: | Order/M1P8, | |

refs: | Panel01/M1P11, | |

ORDClr | ||

def: | Order/M1P8, | |

refs: | Panel01/M1P11, | |

Order | Gated order to Coincidence Unit and SCT | |

def: | Order/M1P8, | |

refs: | CU/M1P5-6, | |

OrderClr | ||

def: | ECP/F4P9, | |

refs: | !!! no references !!! | |

OrderIn | ||

def: | Order/M1P8, | |

refs: | OFL/M3P2-4, | |

OrderSCT | ||

def: | CU/M1P5-6, | |

refs: | TFL/M3P8-10, | |

Order~ | Ungated order to CCU | |

def: | Order/M1P8, | |

refs: | CCU3/R4P3, SCT/M1P7, | |

ORDIG | ||

def: | Order/M1P8, | |

refs: | Panel01/M1P11, | |

ORDIn | ||

def: | Order/M1P8, | |

refs: | Panel01/M1P11, | |

ORDOG | ||

def: | Order/M1P8, | |

refs: | Panel01/M1P11, | |

ORDout | Memory tank n output | |

def: | Panel01/M1P11, | |

refs: | Order/M1P8, | |

PrtBusy | ||

def: | Printer/F4P4-6, | |

refs: | !!! no references !!! | |

R1Clock | Buffered clock for rack R1 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P10, Panel01/R1P11, Panel01/R1P12, Panel01/R1P13, Panel01/R1P2, Panel01/R1P3, Panel01/R1P4, Panel01/R1P5, | |

R1DnDecIn | Write gate to lower panels | |

def: | TDec1/R1P7, | |

refs: | TDist/R1P8, | |

R1DnDecOut | Read gate to lower panels | |

def: | TDec1/R1P7, | |

refs: | TDist/R1P8, | |

R1DnF7+ | Gate to lower tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P6, | |

R1DnF7- | Inverse gate to lower tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P6, | |

R1DnF8+ | Gate to lower tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P6, | |

R1DnF8- | Inverse gate to lower tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P6, | |

R1DnMOBT0 | Memory tank n output | |

def: | Panel01/R1P2, | |

refs: | TDec1/R1P7, | |

R1DnMOBT1 | Memory tank n output | |

def: | Panel01/R1P3, | |

refs: | TDec1/R1P7, | |

R1DnMOBT2 | Memory tank n output | |

def: | Panel01/R1P4, | |

refs: | TDec1/R1P7, | |

R1DnMOBT3 | Memory tank n output | |

def: | Panel01/R1P5, | |

refs: | TDec1/R1P7, | |

R1DnT0Clr | Clear gate to tank 4 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P2, | |

R1DnT0in | Gate input to tank 0 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P2, TDec1/R1P7, | |

R1DnT0out | Gate output of tank 0 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P2, | |

R1DnT1Clr | Clear gate to tank 5 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P3, | |

R1DnT1in | Gate input to tank 1 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P3, TDec1/R1P7, | |

R1DnT1out | Gate output of tank 1 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P3, | |

R1DnT2Clr | Clear gate to tank 6 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P4, | |

R1DnT2in | Gate input to tank 2 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P4, TDec1/R1P7, | |

R1DnT2out | Gate output of tank 2 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P4, | |

R1DnT3Clr | Clear gate to tank 7 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P5, | |

R1DnT3in | Gate input to tank 3 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P5, TDec1/R1P7, | |

R1DnT3out | Gate output of tank 3 | |

def: | TFinal/R1P6, | |

refs: | Panel01/R1P5, | |

R1DnTIn | Buffered gate to lower TFinal | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P6, | |

R1DnTOut | Buffered gate to lower TFinal | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P6, | |

R1MIBs | Buffered MIB to memory panels in this rack | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P10, Panel01/R1P11, Panel01/R1P12, Panel01/R1P13, Panel01/R1P2, Panel01/R1P3, Panel01/R1P4, Panel01/R1P5, | |

R1MOB | Combined output from tanks in this rack | |

def: | TDec1/R1P7, | |

refs: | XFR/M2P11-P12, | |

R1Read | Read gate to rack R1 | |

def: | TDec0/M3P13, | |

refs: | TDec1/R1P7, | |

R1UpDecIn | Write gate to upper panels | |

def: | TDec1/R1P7, | |

refs: | TDist/R1P8, | |

R1UpDecOut | Read gate to upper panels | |

def: | TDec1/R1P7, | |

refs: | TDist/R1P8, | |

R1UpF7+ | Gate to upper tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P9, | |

R1UpF7- | Inverse gate to upper tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P9, | |

R1UpF8+ | Gate to upper tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P9, | |

R1UpF8- | Inverse gate to upper tank decoder | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P9, | |

R1UpMOBT0 | Memory tank n output | |

def: | Panel01/R1P10, | |

refs: | TDec1/R1P7, | |

R1UpMOBT1 | Memory tank n output | |

def: | Panel01/R1P11, | |

refs: | TDec1/R1P7, | |

R1UpMOBT2 | Memory tank n output | |

def: | Panel01/R1P12, | |

refs: | TDec1/R1P7, | |

R1UpMOBT3 | Memory tank n output | |

def: | Panel01/R1P13, | |

refs: | TDec1/R1P7, | |

R1UpT0Clr | Clear gate to tank 0 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P10, | |

R1UpT0in | Gate input to tank 0 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P10, TDec1/R1P7, | |

R1UpT0out | Gate output of tank 0 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P10, | |

R1UpT1Clr | Clear gate to tank 1 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P11, | |

R1UpT1in | Gate input to tank 1 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P11, TDec1/R1P7, | |

R1UpT1out | Gate output of tank 1 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P11, | |

R1UpT2Clr | Clear gate to tank 2 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P12, | |

R1UpT2in | Gate input to tank 2 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P12, TDec1/R1P7, | |

R1UpT2out | Gate output of tank 2 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P12, | |

R1UpT3Clr | Clear gate to tank 3 | |

def: | TDec1/R1P7, | |

refs: | Panel01/R1P13, | |

R1UpT3in | Gate input to tank 3 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P13, TDec1/R1P7, | |

R1UpT3out | Gate output of tank 3 | |

def: | TFinal/R1P9, | |

refs: | Panel01/R1P13, | |

R1UpTIn | Buffered gate to upper TFinal | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P9, | |

R1UpTOut | Buffered gate to upper TFinal | |

def: | TDist/R1P8, | |

refs: | TFinal/R1P9, | |

R1Write | Write gate to rack R1 | |

def: | TDec0/M3P13, | |

refs: | TDec1/R1P7, | |

R2 | Coincidence Detected to Computer | |

def: | MCU/M1P2-4, | |

refs: | CCU4/R5P7, CCU9/R5P8, Mpier/R4P13, Printer/F4P4-6, Tape/F4P7+8, | |

R2Clock | Buffered clock for rack R2 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P10, Panel01/R2P11, Panel01/R2P12, Panel01/R2P13, Panel01/R2P2, Panel01/R2P3, Panel01/R2P4, Panel01/R2P5, | |

R2DnDecIn | Write gate to lower panels | |

def: | TDec1/R2P7, | |

refs: | TDist/R2P8, | |

R2DnDecOut | Read gate to lower panels | |

def: | TDec1/R2P7, | |

refs: | TDist/R2P8, | |

R2DnF7+ | Gate to lower tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P6, | |

R2DnF7- | Inverse gate to lower tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P6, | |

R2DnF8+ | Gate to lower tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P6, | |

R2DnF8- | Inverse gate to lower tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P6, | |

R2DnMOBT0 | Memory tank n output | |

def: | Panel01/R2P2, | |

refs: | TDec1/R2P7, | |

R2DnMOBT1 | Memory tank n output | |

def: | Panel01/R2P3, | |

refs: | TDec1/R2P7, | |

R2DnMOBT2 | Memory tank n output | |

def: | Panel01/R2P4, | |

refs: | TDec1/R2P7, | |

R2DnMOBT3 | Memory tank n output | |

def: | Panel01/R2P5, | |

refs: | TDec1/R2P7, | |

R2DnT0Clr | Clear gate to tank 4 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P2, | |

R2DnT0in | Gate input to tank 0 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P2, TDec1/R2P7, | |

R2DnT0out | Gate output of tank 0 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P2, | |

R2DnT1Clr | Clear gate to tank 5 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P3, | |

R2DnT1in | Gate input to tank 1 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P3, TDec1/R2P7, | |

R2DnT1out | Gate output of tank 1 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P3, | |

R2DnT2Clr | Clear gate to tank 6 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P4, | |

R2DnT2in | Gate input to tank 2 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P4, TDec1/R2P7, | |

R2DnT2out | Gate output of tank 2 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P4, | |

R2DnT3Clr | Clear gate to tank 7 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P5, | |

R2DnT3in | Gate input to tank 3 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P5, TDec1/R2P7, | |

R2DnT3out | Gate output of tank 3 | |

def: | TFinal/R2P6, | |

refs: | Panel01/R2P5, | |

R2DnTIn | Buffered gate to lower TFinal | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P6, | |

R2DnTOut | Buffered gate to lower TFinal | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P6, | |

R2MIBs | Buffered MIB to memory panels in this rack | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P10, Panel01/R2P11, Panel01/R2P12, Panel01/R2P13, Panel01/R2P2, Panel01/R2P3, Panel01/R2P4, Panel01/R2P5, | |

R2MOB | Combined output from tanks in this rack | |

def: | TDec1/R2P7, | |

refs: | XFR/M2P11-P12, | |

R2Read | Read gate to rack R2 | |

def: | TDec0/M3P13, | |

refs: | TDec1/R2P7, | |

R2UpDecIn | Write gate to upper panels | |

def: | TDec1/R2P7, | |

refs: | TDist/R2P8, | |

R2UpDecOut | Read gate to upper panels | |

def: | TDec1/R2P7, | |

refs: | TDist/R2P8, | |

R2UpF7+ | Gate to upper tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P9, | |

R2UpF7- | Inverse gate to upper tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P9, | |

R2UpF8+ | Gate to upper tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P9, | |

R2UpF8- | Inverse gate to upper tank decoder | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P9, | |

R2UpMOBT0 | Memory tank n output | |

def: | Panel01/R2P10, | |

refs: | TDec1/R2P7, | |

R2UpMOBT1 | Memory tank n output | |

def: | Panel01/R2P11, | |

refs: | TDec1/R2P7, | |

R2UpMOBT2 | Memory tank n output | |

def: | Panel01/R2P12, | |

refs: | TDec1/R2P7, | |

R2UpMOBT3 | Memory tank n output | |

def: | Panel01/R2P13, | |

refs: | TDec1/R2P7, | |

R2UpT0Clr | Clear gate to tank 0 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P10, | |

R2UpT0in | Gate input to tank 0 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P10, TDec1/R2P7, | |

R2UpT0out | Gate output of tank 0 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P10, | |

R2UpT1Clr | Clear gate to tank 1 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P11, | |

R2UpT1in | Gate input to tank 1 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P11, TDec1/R2P7, | |

R2UpT1out | Gate output of tank 1 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P11, | |

R2UpT2Clr | Clear gate to tank 2 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P12, | |

R2UpT2in | Gate input to tank 2 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P12, TDec1/R2P7, | |

R2UpT2out | Gate output of tank 2 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P12, | |

R2UpT3Clr | Clear gate to tank 3 | |

def: | TDec1/R2P7, | |

refs: | Panel01/R2P13, | |

R2UpT3in | Gate input to tank 3 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P13, TDec1/R2P7, | |

R2UpT3out | Gate output of tank 3 | |

def: | TFinal/R2P9, | |

refs: | Panel01/R2P13, | |

R2UpTIn | Buffered gate to upper TFinal | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P9, | |

R2UpTOut | Buffered gate to upper TFinal | |

def: | TDist/R2P8, | |

refs: | TFinal/R2P9, | |

R2Write | Write gate to rack R2 | |

def: | TDec0/M3P13, | |

refs: | TDec1/R2P7, | |

RdrBusy | ||

def: | Tape/F4P7+8, | |

refs: | !!! no references !!! | |

ResetFF10 | Reset FF1 after shifting | |

def: | CCU3/R4P3, | |

refs: | CCU8/R5P11, | |

Rpulse | Coincidence Detected pulse | |

def: | CU/M1P5-6, | |

refs: | MCU/M1P2-4, | |

S1 | Stimulating Pulse to Coincidence Unit | |

def: | MCU/M1P2-4, | |

refs: | CU/M1P5-6, | |

S2 | Stimulating Pulse to Computer | |

def: | MCU/M1P2-4, | |

refs: | CCU10/R3P13, CCU2/R4P2, CCU5/R4P5, CCU9/R5P8, Controls/M2P10, Printer/F4P4-6, Starter/F410-13, | |

SCT | Gated output to Coincidence Unit | |

def: | SCT/M1P7, | |

refs: | CU/M1P5-6, | |

SCTCG | Clear Gate to SCT for transfers | |

def: | MCU/M1P2-4, | |

refs: | SCT/M1P7, | |

SCTHA-A | ||

def: | SCT/M1P7, | |

refs: | HalfAdder1/M1P9, | |

SCTHA-B1 | ||

def: | SCT/M1P7, | |

refs: | HalfAdder1/M1P9, | |

SCTHA-B2 | ||

def: | SCT/M1P7, | |

refs: | HalfAdder1/M1P9, | |

SCTHA-C | ||

def: | HalfAdder1/M1P9, | |

refs: | SCT/M1P7, | |

SCTHA-Sum | ||

def: | HalfAdder1/M1P9, | |

refs: | SCT/M1P7, | |

SCTIG | SCT Input gate for transfers | |

def: | MCU/M1P2-4, | |

refs: | SCT/M1P7, | |

SCTOne | Increment pulse to SCT | |

def: | MCU/M1P2-4, | |

refs: | !!! no references !!! | |

SCTTA1 | ||

def: | Panel01/M1P13, | |

refs: | SCT/M1P7, | |

SCTTClk | ||

def: | SCT/M1P7, | |

refs: | Panel01/M1P13, | |

SCTTClr | ||

def: | SCT/M1P7, | |

refs: | Panel01/M1P13, | |

SCTTIG | ||

def: | SCT/M1P7, | |

refs: | Panel01/M1P13, | |

SCTTIn | ||

def: | SCT/M1P7, | |

refs: | Panel01/M1P13, | |

SCTTOG | ||

def: | SCT/M1P7, | |

refs: | Panel01/M1P13, | |

SCTTOut | Memory tank n output | |

def: | Panel01/M1P13, | |

refs: | !!! no references !!! | |

SCT~ | ||

def: | SCT/M1P7, | |

refs: | !!! no references !!! | |

SEP2 | ||

def: | Starter/F410-13, | |

refs: | Controls/M2P10, | |

SingleEP | ||

def: | Controls/M2P10, | |

refs: | MCU/M1P2-4, | |

Start | ||

def: | Controls/M2P10, | |

refs: | Starter/F410-13, | |

Starter | ||

def: | Starter/F410-13, | |

refs: | OCod/M2P8+9, | |

Starter- | ||

def: | Starter/F410-13, | |

refs: | Controls/M2P10, OCod/M2P8+9, Order/M1P8, | |

Stop- | ||

def: | Controls/M2P10, | |

refs: | MCU/M1P2-4, | |

StopOnea | Suppress SCT increments while waiting nfor Reader | |

def: | Tape/F4P7+8, | |

refs: | CCU10/R3P13, | |

StopOnec | suppress SCT increment while busy | |

def: | Printer/F4P4-6, | |

refs: | CCU10/R3P13, | |

Stop_One- | Suppress SCT increment during transfers | |

def: | CCU10/R3P13, | |

refs: | SCT/M1P7, | |

TCTA1 | ||

def: | Panel01/R4P7, | |

refs: | TCT/R4P6, | |

TCTClk | ||

def: | TCT/R4P6, | |

refs: | Panel01/R4P7, | |

TCTClr | ||

def: | TCT/R4P6, | |

refs: | Panel01/R4P7, | |

TCTIG | ||

def: | TCT/R4P6, | |

refs: | Panel01/R4P7, | |

TCTIn | ||

def: | TCT/R4P6, | |

refs: | Panel01/R4P7, | |

TCTOG | ||

def: | TCT/R4P6, | |

refs: | Panel01/R4P7, | |

TCTout | Memory tank n output | |

def: | Panel01/R4P7, | |

refs: | !!! no references !!! | |

Trig0 | ||

def: | Ctr/M1P7, | |

refs: | !!! no references !!! | |

X1 | Right shift enable | |

def: | ASU1/R3P3, | |

refs: | ASU2/R3P2, | |

X2 | Right shift disable | |

def: | ASU1/R3P3, | |

refs: | ASU2/R3P2, | |

X3 | Left shift disable | |

def: | ASU1/R3P3, | |

refs: | ASU2/R3P2, | |

X4 | Left shift enable | |

def: | ASU1/R3P3, | |

refs: | ASU2/R3P2, | |

XFR1-A1 | ||

def: | Panel01/M2P13, | |

refs: | XFR/M2P11-P12, | |

XFR1-Clk | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P13, | |

XFR1-Clr | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P13, | |

XFR1-IG | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P13, | |

XFR1-In | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P13, | |

XFR1-OG | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P13, | |

XFR1-Out | Memory tank n output | |

def: | Panel01/M2P13, | |

refs: | !!! no references !!! | |

XFR2-A1 | ||

def: | Panel01/M2P14, | |

refs: | XFR/M2P11-P12, | |

XFR2-Clk | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P14, | |

XFR2-Clr | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P14, | |

XFR2-IG | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P14, | |

XFR2-In | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P14, | |

XFR2-OG | ||

def: | XFR/M2P11-P12, | |

refs: | Panel01/M2P14, | |

XFR2-Out | Memory tank n output | |

def: | Panel01/M2P14, | |

refs: | !!! no references !!! |