Initial Orders Loader
Timing Control Tank
Tank Address Decoder 0
Tank Address Decoder 1
Tank Address Distribution
Tank Address Flashing Units
Tank Address Decoding Final Stage
Tape Reader
Test Frigs
Transfer Unit

The Order Tank is a short (18 bit) mercury tank with recirculation.

It holds the current instruction after it has been read from memory in Stage 1. The order bits (13-17), tank number bits (7-11), length (1) and half-word (2) bits are stored in the various flashing units, but the address within a tank (2-6) bits are needed repeatedly for comparison in the Coincidence Unit.

The Order Tank is cleared at the end of Stage2, when the falling edge of G13 sets the flipflop ff1. The positive output of this is ORed with the coincidence gate (CG+) and inverted to close the recirculation gate. The coincidence gate, G12 are used to gate the MIB into the tank. The output of the tank is gated with G13 and Boot- so that this is fed to the Coincidence Unit during Stage 2 of normal instructions.

During the loading of Initial Instructions, the Boot- line drops and prevents the output from reaching the CU. Under these conditions, the SCT is used as the memory address.

The signal Order~ is provided purely for monitoring in the simulator and need not be provided in the replica, other than as a test point.

The design here is conjecture. Only a brief textual description is given in the Report, but it is fairly clear as to the basic function.